In producing integrated circuits for power applications in the prior art, it is typical to use source and drain diffusions that are interconnected to form one or a few large transistors from many individual source and drain regions. Devices are often designed using a plurality of these lateral diffusions which are then coupled together to make a single large current capacity device, or several large current carrying devices. In order to achieve the desired performance in such a device, a very low resistance interconnection structure for the plurality of diffusions is required. Other applications may likewise require the interconnection of many devices in parallel where a very low resistance interconnection structure is desirable.
In the prior art, single and double level metallization schemes are used to make the connections between the various diffusions and thereby form the large devices required for circuits. Because the lengths of the metal runs are quite long in some integrated circuits, current distribution tends to become nonuniform across the devices. As a further consequence, debiasing also occurs along the metal lengths, which results in different areas of the device operating at different potentials. Non-uniform operation of the device results from this metal debiasing and the various diffused areas switch at different instants, causing nonuniform current distribution.
FIG. 1 depicts a cross sectional view of a prior art plastic encapsulated integrated circuit. In FIG. 1, a completed silicon integrated circuit die 17 is attached to the die pad of lead frame 11 by an epoxy or die attach compound or other die attach method. The leadframe and die assembly are placed in a automated wire bonding station, and bond wires 13 are attached between the leads of the lead frame 11 and bond pad areas defined in the surface of the uppermost layer of metallization on die 17. The wire bonded die 17 and leadframe 11 are then placed in a mold press for encapsulation. In the mold press, package 15 is formed of a thermoplastic resin mold compound which is forced under heat and pressure through runners and into a cavity surrounding the die 17, the die pad, and the bond wires 13, and partially including the leads of the leadframe 11. The resulting package then covers the die 17, bond wires 13, and the die pad, so that the packaged IC is a plastic package with a plurality of leads extending out of it, typically the leads come out in two lines, as in the dual in-line package, or on each of the four sides, as for the quad flat pack (QFP) packages and small outline packages (SOIC).
Although the conventional two level metallization schemes of the prior art can be optimized to reduce the current debiasing problems, for fabricating large devices carrying large current loads the problems with debiasing remain. One approach to a two metal interconnection scheme for an LDMOS power device composed of many diffusion stripes is described in a co-pending U.S. patent application entitled "A Method for Current Ballasting and Busing over Active Device Area Using a Multi-Level Conductor Process", TI-16545, U.S. application Ser. No. 07/850,601, assigned to Texas Instruments Incorporated and herein incorporated by reference. Although the techniques and structures for placing the contacts and vias in a two level metal interconnection scheme described in this earlier patent application will reduce the debiasing effects as much as possible using conventional metallization techniques, the debiasing and current distribution problems persist for large transistors having long interconnect metal lengths.
Further problems arise as higher current capacity devices are designed using the prior art techniques. The nonuniformity of current distribution associated with debiasing can lead to so called "hot spots", areas where localized current exceeds the thermal power limits of the device, and premature failure locations are the result. These premature failures further result in lower peak current capacity ratings for the devices and a reduced safe operating area rating.
As a means to reduce the interconnection resistance of these power devices, a thick level metallization layer plated over the conventional first and second level metal levels has been proposed. As a conductor material, copper has been suggested as described in some of the co-pending patent applications, identified as related applications above. For example, in constructing high power lateral devices using MOS technology, many lateral drain and source diffusion regions are created and then coupled together. Adding a thick level copper interconnection metal to the conventional aluminum interconnection structures has been found to reduce the on resistance of the resulting devices, eliminate non-uniform switching, hot spots, and electromigration, and expand the current carrying capacity and safe operation area for these devices.
To add the third level metal layer to a conventional integrated circuit, the integrated circuit die is given a protective overcoat oxide layer, or alternatively nitride or oxinitride layer, and removed from the conventional processing area. A thick copper layer is then formed at the top surface using an electroplating or an electroless plating technique. The copper interconnect is formed either in direct physical contact with the aluminum second level metal, or optionally an isolation layer is used, vias are formed, and the aluminum busses are selectively coupled to busses formed of the thick level metal copper layer.
The copper surface level interconnection process provides a low resistance solution to many of the problems with the prior art. The use of the copper interconnect level eliminates the debiasing caused by the resistance of long runs of conventional aluminum interconnect levels, because the resistance of the new structure is so low that there is little or no measurable debiasing effect. Further, non-uniform switching and electromigration problems are also practically eliminated by the low resistance interconnection structure that results.
However, problems remain in packaging the copper surface level interconnect devices. In the prior art, packaging integrated circuits in conventional plastic encapsulation packages which have reactive or active materials on them has been avoided. Copper is such a material. The plastic packages commonly used in such packaging are not hermetic packages. If a volatile or reactive material is used within the package, therefore, it may react with moisture, sodium or oxygen contaminants that enter the package. The integrated circuit package is also thermally cycled during use and the heat may catalyze the reaction of the materials with the contaminants, and thereby exacerbate the formation of compounds that damage the device or cause failures in the devices while in use, such as shorting compounds or corrosion sites. The conventional technique for overcoming these problems is to use passivation materials over the metal layers within the integrated circuit. Nitrides and oxides can be deposited on all surfaces of the reactive material and the layer of nitride or oxide used to contain the reactive material within an inert layer of stable material. For example, the conventional first and second aluminum metal layers are typically passivated with nitride.
The copper interconnection levels used in these low resistance devices incorporating the invention are very thick layers. Some devices have been designed with up to 50 microns of copper bussing over the top of the conventional structure. This copper surface level interconnect layer is essentially similar to a huge rectangular bar of copper placed over the conventional wafer. Existing techniques for adding passivation to materials cannot successfully cover and passivate such a large step distance from the lower layers. Accordingly, a need thus exists for a method and apparatus which provides a reliable integrated circuit device with a plated copper interconnection surface layer encapsulated in a plastic package.